1. Field of the Invention
This invention relates to a high density electrically erasable and programmable nonvolatile memory cells and more particularly to a high density nonvolatile memory cell utilizing a stacked gate floating gate transistor, a pass transistor and a floating diffusion region, and a process for making such a cell.
2. Description of the Prior Art
In semiconductor memory devices which are nonvolatile, information that is stored is not lost when the power supply is removed. Memory devices of this type include the EPROM (Erasable Programmable Read-Only Memory) and the EEPROM (Electrically Erasable and Programmable Read-Only Memory). A typical EPROM uses single transistor cell which has two stacking polysilicon gates. The upper gate is a control gate and the bottom gate is a floating gate disposed between the control gate and the substrate. Programming or writing is accomplished by injection of hot electrons from the channel region through an oxide layer in response to high applied drain voltage and control gate voltage. The injected electrons are stored in the floating gate until an erasing action is taken. Erasure is accomplished by photoemission of the stored electrons from the floating gate to the control gate and the substrate. Practical EPROM cell programming requires high channel current, high programming voltages at the drain as well as at the control gate, and therefore cannot be programmed using a single standard five-volt power supply. For standard EPROM products, an additional power supply of higher voltage is required for programming.
Most conventional EEPROM products are made using dual element cells, which consist of two individual transistors, namely, a select transistor and a floating gate transistor. Programming and erasure are accomplished by means of Fowler-Nordheim effect which allows electrons to tunnel through an insulating layer between two electrodes. Information is stored by putting either positive charges or negative charges on a floating gate. During a read operation, the charge status of the EEPROM cell is detected by sensing the current that passes a select transistor. Conventional EEPROM cells require a select transistor and an area to situate a tunnel window, thus requiring a larger cell size as compared to an EPROM cell. Although the Fowler-Nordheim tunneling also requires high voltages, since they need not consume high current, the required high voltages can be provided by use of an on-chip voltage pump, which elevates the standard five-volt supply voltage to a higher level. Generally, an EPROM cell requires less area to implement than does an EEPROM cell, but the EPROM cell requires an external power supply for the programming operation.
It is highly desirable to produce a nonvolatile memory cell which has a small cell size and which can be programmed with the standard five-volt power supply. A prior art has attempted to achieve this by utilizing a short channel EPROM cell. As described in the article entitled "A Single Transistor EEPROM Cell and Its Implementation in A 512K CMOS EEPROM" by Satyen Mukherjee et al., which appeared in the IEEE Technical Digest of IEDM 1985, pages 616-619, a stacked gate cell is described which is said to be programmable with less than five volts on the drain. Programming may be achieved with the five volts by utilizing a relatively short channel length, however uncontrolled drain-to-source breakdown due to process related gate length variations renders the cell to have the disadvantage that when programming other bits sitting on the same bit line, the unintended cells may be deprogrammed, such phenomenon being known as programming disturbance. Accordingly, the challenge is to provide a nonvolatile memory cell which can be programmed with five volts and which will not suffer from programming disturbance. It is additionally desirable to provide an EEPROM memory cell which can tolerate the undesired overerased condition, in which positive charges are stored in the floating gate due to excessive tunneling. Without a select transistor, under a normal read mode operation, such a condition can cause current to leak through unaddressed cells along a selected bit line and therefore can be confused with the real cell current of a selected bit.
To overcome the programming disturbance and false read problems noted above, an attempt has been made by using two-transistor EEPROM cells utilizing a split gate. A typical split-gate flash EEPROM cell has been described in an article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology" by Gheorghe Samachisa et al. which appeared in the IEEE Journal of Solid State Circuits Vol SC-22, No. 5, October 1987. This type of split-gate cell has a disadvantage of needing high drain voltage for programming and it does not have the capability for byte erase.
The need for programming an EEPROM memory cell using lower voltages has been addressed in U.S. Pat. No. 4,698,787 to Mukherjee et al., issued Oct. 6, 1987. The Mukherjee et al patent discloses a cell in which cell programming can be achieved by hot electron injection by raising the drain to about 5 volts, while the control gate is pulsed at an amplitude of approximately 10 to 12 volts. Although this represents an improvement in programming voltage required, because of the construction of the cell in Mukherjee et al., arrays produced with such cells can only have the capability of providing either byte erase or block erase, but not both utilizing a single array structure. From their circuit of FIG. 5d and the partial view of the array layout illustrated in FIG. 5c, as shown in the patent, it appears that the resistive loading in each cell is high and would limit the low drain programming voltage operations.